Phase-locked loop (PLL) and delay-locked loop (DLL) integrated circuits are frequently used to generate highly accurate internal clock signals on integrated circuit substrates (e.g., chips). However, such conventional PLL and DLL integrated circuits are frequently susceptible to unwanted clock skew and jitter as clock speed and circuit integration levels are increased and supply and substrate noise becomes more significant. In particular, PLLs typically suffer from phase error accumulation that may persist for long periods of time in noisy environments, whereas DLLs may have lower jitter performance because phase error accumulation does not occur. Thus, DLLs may offer an important alternative to PLLs in cases where a reference clock signal comes from a low-jitter source. However, DLLs typically cannot be used in applications where frequency tracking is required, such as frequency synthesis and clock recovery. DLLs may also be difficult to design for environments that experience significant process, voltage and temperature (PVT) variations.
PLL and DLL self-biasing techniques, which have been developed to address some of these limitations associated with conventional PLL and DLL integrated circuits, can provide a bandwidth that tracks operating frequency. This tracking of the bandwidth typically supports a broad frequency range and may minimize supply and substrate noise-induced jitter. These and other aspects of conventional self-biasing techniques are more fully described in an article by J. Maneatis, entitled “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1723–1732, November (1996).
FIG. 1 illustrates a conventional self-biased phase-locked loop (PLL) integrated circuit 100. This PLL integrated circuit 100 includes: a phase-frequency detector 102, first and second charge pumps 104, 106, a low pass filter 108 (containing a large capacitor 116), a bias generator 110, a voltage-controlled oscillator 112 and a divide-by-N feedback circuit 114, connected as illustrated. The inclusion of a pair of charge pumps 104, 106 supports a self-biasing configuration within the PLL integrated circuit 100 by allowing all bias currents and voltages to be referenced to other generated bias voltages and currents, which are established by the operating frequency. FIG. 2 illustrates a conventional self-biased delay-locked loop (DLL) integrated circuit 200. This DLL integrated circuit 200 includes: a phase-frequency detector 202, a charge pump 204, a low pass filter 206 (containing a large capacitor 212), a bias generator 210 and a voltage-controlled delay line (VCDL) 208, connected as illustrated. As will be understood by those skilled in the art, the feedback of the bias signal VBN to an input of the charge pump 204 supports a self-biasing configuration within the DLL integrated circuit 200. FIGS. 1 and 2 are equivalent to FIGS. 1 and 5 of U.S. Pat. No. 5,727,037 to Maneatis. Additional PLL integrated circuits that utilize multiple charge pumps to support self-biased operation are disclosed in U.S. Pat. Nos. 6,329,882 and 6,894,569 to Fayneh et al.
An integrated circuit chip that supports high speed serial/deserial (SERDES) operations may include many (e.g., >10) PLL integrated circuits that must run at target speeds (e.g., multi-GHZ frequencies) if the chip is to pass speed testing upon manufacture. One conventional technique to perform speed testing of PLL integrated circuits includes dividing down a high frequency PLL output clock signal by an integer N and measuring the number of cycles of the divided clock signal over a reference time interval ((cycles/time)N=PLL clock frequency). As will be understood by those skilled in the art, the start and stop times of the reference time interval may be established by a reference counter that is responsive to a reference clock signal and the number of cycles of the divided clock signal may be measured by a target counter coupled to an output of the reference counter, which sets the start and stop time points. Unfortunately, such conventional speed testing techniques typically cannot be performed at the wafer level (e.g., prior to chip packaging) and may require the use of relatively large counters and long test times to identify relatively small fluctuations in the frequency of a PLL clock signal relative to the target frequency. Accordingly, to save manufacturing costs and simplify test board design, speed testing of PLL integrated circuits should be performed as simply and as early in the chip manufacturing process as possible (e.g., at the wafer level) and should avoid the use of large test circuits (e.g., large counters).